1/9 september 2001 n 5v tolerant inputs and outputs n high speed : t pd = 8.0 ns (max.) at v cc =3v n power down protection on inputs and outputs n symmetrical output impedance: |i oh |=i ol = 24ma (min) at v cc =3v n pci bus levels guaranteed at 24 ma n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2.0v to 3.6v (1.5v data retention) n pin and function compatible with 74 series 540 n latch-up performance exceeds 500ma (jesd 17) n esd performance: hbm > 2000v (mil std 883 method 3015); mm > 200v description the 74lcx540 is a low voltage cmos octal bus buffer (inverted) fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. it is ideal for low power and high speed 3.3v applications; it can be interfaced to 5v signal environment for both inputs and outputs. the 3 state control gate operates as two input and such that if either g1 and g2 are high, all eight outputs are in the high impedance state. in order to enhance pc board layout the 74lcx540 offers a pinout having inputs and outputs on opposite sides of the package. it has same speed performance at 3.3v than 5v ac/act family, combined with a lower power consumption. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74lcx540 low voltage cmos octal bus buffer (3-state) with 5v tolerant inputs and outputs pin connection and iec logic symbols order codes package tube t & r sop 74LCX540M 74LCX540Mtr tssop 74lcx540ttr tssop sop
74lcx540 2/9 input and output equivalent circuit pin description truth table x : don't care z : high impedance absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied 1) i o absolute maximum rating must be observed 2) v o < gnd pin no symbol name and function 1, 19 g1, g2 output enable inputs 2, 3, 4, 5, 6, 7, 8, 9 a1 to a8 data inputs 18, 17, 16, 15, 14, 13, 12, 11 y1 to y8 data outputs 10 gnd ground (0v) 20 v cc positive supply voltage input output g1 g2 an yn hxxz xhxz llhl lllh symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage (off state) -0.5 to +7.0 v v o dc output voltage (high or low state) (note 1) -0.5 to v cc + 0.5 v i ik dc input diode current -50 ma i ok dc output diode current (note 2) -50 ma i o dc output current 50 ma i cc dc supply current per supply pin 100 ma i gnd dc ground current per supply pin 100 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c
74lcx540 3/9 recommended operating conditions 1) truth table guaranteed: 1.5v to 3.6v 2) v in from 0.8v to 2v at v cc = 3.0v dc specifications symbol parameter value unit v cc supply voltage (note 1) 2.0 to 3.6 v v i input voltage 0 to 5.5 v v o output voltage (off state) 0 to 5.5 v v o output voltage (high or low state) 0 to v cc v i oh ,i ol high or low level output current (v cc = 3.0 to 3.6v) 24 ma i oh ,i ol high or low level output current (v cc = 2.7v) 12 ma t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 2) 0 to 10 ns/v symbol parameter test condition value unit v cc (v) -40 to 85 c -55 to 125 c min. max. min. max. v ih high level input voltage 2.7 to 3.6 2.0 2.0 v v il low level input voltage 0.8 0.8 v v oh high level output voltage 2.7 to 3.6 i o =-100 m av cc -0.2 v cc -0.2 v 2.7 i o =-12 ma 2.2 2.2 3.0 i o =-18 ma 2.4 2.4 i o =-24 ma 2.2 2.2 v ol low level output voltage 2.7 to 3.6 i o =100 m a 0.2 0.2 v 2.7 i o =12 ma 0.4 0.4 3.0 i o =16 ma 0.4 0.4 i o =24 ma 0.55 0.55 i i input leakage current 2.7 to 3.6 v i = 0 to 5.5v 5 5 m a i off power off leakage current 0 v i or v o = 5.5v 10 10 m a i oz high impedance output leakage current 2.7 to 3.6 v i =v ih or v il v o = 0 to v cc 5 5 m a i cc quiescent supply current 2.7 to 3.6 v i =v cc or gnd 10 10 m a v i or v o = 3.6 to 5.5v 10 10 d i cc i cc incr. per input 2.7 to 3.6 v ih =v cc - 0.6v 500 500 m a
74lcx540 4/9 dynamic switching characteristics 1) number of outputs defined as ono. measured with on-1o outputs switching from high to low or low to high. the remaining output is measured in the low state. ac electrical characteristics 1) skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch- ing in the same direction, either high or low (t oslh =|t plhm -t plhn |, t oshl =|t phlm -t phln |) 2) parameter guaranteed by design capacitive characteristics 1) c pd is defined as the value of the ic's internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /8 (per buffer) symbol parameter test condition value unit v cc (v) t a =25 c min. typ. max. v olp dynamic low level quiet output (note 1) 3.3 c l = 50pf v il =0v,v ih = 3.3v 0.8 v v olv -0.8 symbol parameter test conditi on value unit v cc (v) c l (pf) r l ( w ) t s = t r (ns) -40 to 85 c -55 to 125 c min. max. min. max. t plh t phl propagation delay time 2.7 50 500 2.5 1.5 9.0 1.5 9.0 ns 3.0 to 3.6 1.5 8.0 1.5 8.0 t pzl t pzh output enable time 2.7 50 500 2.5 1.5 9.5 1.5 9.5 ns 3.0 to 3.6 1.5 8.5 1.5 8.5 t plz t phz output disable time 2.7 50 500 2.5 1.5 8.5 1.5 8.5 ns 3.0 to 3.6 1.5 7.5 1.5 7.5 t oslh t oshl output to output skew time (note1, 2) 3.0 to 3.6 50 500 2.5 1.0 1.0 ns symbol parameter test condition value unit v cc (v) t a =25 c min. typ. max. c in input capacitance 3.3 v in = 0 to v cc 6pf c out output capacitance 3.3 v in = 0 to v cc 12 pf c pd power dissipation capacitance (note 1) 3.3 f in = 10mhz v in = 0 or v cc 25 pf
74lcx540 5/9 test circuit c l = 50 pf or equivalent (includes jig and probe capacitance) r l = r1 = 500 w or equivalent r t =z out of pulse generator (typically 50 w ) waveform 1 : propagation delays (f=1mhz; 50% duty cycle) test switch t plh ,t phl open t pzl ,t plz 6v t pzh ,t phz gnd
74lcx540 6/9 waveform 2 : output enable and disable time (f=1mhz; 50% duty cycle)
74lcx540 7/9 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45 (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s8 (max.) so-20 mechanical data po13l
74lcx540 8/9 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0089 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0 8 0 8 l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
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